AMD Ryzen 9 4950X should offer 16 Zen 3 cores with upto 4.8 GHz

The exact name of the chip is not yet known. But according to a new report, the fastest next-gen AMD Ryzen desktop processor should have 16 cores and 32 threads clocked at up to 4.8GHz and some interesting new features. Sentence.

Just a few weeks ago, AMD more or less officially confirmed that the Ryzen 4000 “Vermeer” desktop processors based on Zen 3 architecture will hit the market this year. Now Igor Vallossek has an exclusive report on German media. German media Will reveal a lot of information about the flagship processor. Which he previously called the Ryzen 9 4950X. The name of the product has not yet been determined.

Accordingly, the new processor remains the same as the Ryzen 9 3950X with 16 cores and 32 threads. The base frequency has not changed at 3.5 GHz. But the clock speed in acceleration mode is increased to 4.8 GHz. On paper, this sounds like a small step forward, but performance per MHz should see a noticeable increase thanks to Zen 3 – rumored you can expect 15 to 17 percent more performance over Zen 2. AMD is still using the tried and tested AM4 socket. while motherboards with a brand new chipset may be needed.

|New features and an interesting changelog

When Intel introduced the 10th generation processors, one of the related innovations was separate Vcore optimization for each individual core. That is, what is called core voltage regulation. This is exactly what Intel has managed to squeeze truly acceptable performance out of a truly old and flawed structure. This feature will also be interesting for overclockers. And it will be interesting to see how it integrates into the Ryzen Master Tool.

This is exactly where AMD like Intel will now start, as the ComboAM4v2PI 1.0.6.0 changelog tells us, even if you have already reached version 8. I already had the meaning of the numbers of the respective minor in the article “AMD UEFI Inside: What’s Really Behind AGESA, PSP (Platform Security Processor) and, above all, ComboPI?” explained.

The first entry is interesting here, which describes exactly this function. The abbreviations in square brackets denote the respective chips, i.e. VMR for Vermeer, RN for Renoir, etc. The entry for Cezanne (CZN) ultimately shows that executable copies already exist for this APU.

In addition, TXCLK gating can be found in the firmware through the port. It indicating improved efficiency. Intelligent timing management techniques are often used to minimize activity in precisely those parts of the circuit that add nothing to the overall result for that particular timing cycle. This clock control reduces dynamic performance by preventing circuit logic that is not used in a particular clock cycle from switching, primarily in that clock cycle.

In addition, it prevents synchronization in cases where new data is not generated or in which this data should not be used by subsequent logic in a certain clock cycle. These gating techniques result in significantly lower dynamics and overall power consumption of the part-load circuit.

|New BIOS entry

The new BIOS entry Enable VCN / FCLK deep sleep is also suitable for this. That is, there is another power saving option which, by the way, is not assigned to a specific model and which may even benefit all processors and APUs in the future. If VCN stands for Video Core Next, then this also applies as an add-on feature to an APU with an integrated graphics unit.

The entry Add NVME RT d3 support is also very interesting because in Runtime D3 (RTD3) the NVMe drive controller is disconnected from the actual operating voltage. Additional supply voltages may or may not continue to be provided (“auxiliary power”). For PCI Express RTD3, this is the so-called current state of D3cold. It’s always good for mobile devices. The rest of the entries are also not boring. But mainly about Renoir and various improvements (tweaking).